(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device such as a static induction transistor and a semiconductor integrated circuit device in which such static induction transistor or transistors are integrated.
(b) Description of the Prior Art
Conventional method of manufacturing a static induction transistor or a static induction transistor logic device (hereinafter referred to as SITL device) usually comprises the following steps: (1) forming an aperture in the SiO.sub.2 film covering the entire surface of a semiconductor an aperture for doping a gate-forming-impurity so as to surround a channel region; thereafter, (2) forming a gate region by selectively diffusing the impurity through said aperture and at the same time therewith defining a region which will serve as a source region surrounded by said gate region; next, (3) after aligning a diffusion mask relative to the gate region, forming the source region within said region adapted to become the source region by selectively diffusing an impurity; and (4) after aligning an etching mask relative to said gate region, said source region and a drain region, forming contact apertures for these respective regions, and forming a gate contact, a source contact and a drain contact.
According to the conventional method described above, it was necessary to perform mask alignments twice for the gate region when the source region and the source contact portion are formed. Thus, this method not only has been troublesome and complicated in terms of steps, but also there has been required a surplus area on the surface of the substrate to provide for some marginal area for mask alignments. Accordingly, there has been a limitation to the minuteness of the circuit structure of the device, and the packing density has been limited greatly. Also, there has been the further inconvenience that, in order to establish self-alignment of the source region and the gate region, the number of masking steps had to be increased.